G. Munirathnam

G MUNIRATHNAM

Name: G MUNIRATHNAM

Designation: Assistant Professor (Ad-hoc)

Experience: 16 years

Specialization: VLSI system Design

Areas of Interest: Low power VLSI, Design for Testability

Address: 5Rajulakandriga (V), Gundrarajukuppam (P), Nagari (M), Chittoor (D)

Email-Id: munirathnam.ece@jntua.ac.in

muni.446446@gmail.com

Mobile-No: +91 9966418874

Career Objective: Quest to work in a very competitive, research and professional environment that gives a scope for learning the latest and emerging technologies.

EDUCATIONAL PROFILE:

  • Ph.D. (VLSI) pursuing from JNTUA, Anantapuramu
  • M.Tech. (VLSI System Design) from SITAMS, Chittoor(JNTUA, Ananthapuramu) in November 2009 with First Class.
  • B.Tech. (Electronics & Communication Engineering) from SITAMS, Chittoor (JNTUA, Ananthapuramu) in July 2005 with Second Class.
  • IPE(MPC). From APSWR Jr College, Ramakuppam in 2001 with First class.
  • SSC. From Z.P.High School, Satrawada in 1999 with First class.

WORKING EXPERIENCE: (UP TO: 15.11.2023) (16 YEARS )

  • At present I have been with JNTUA College of Engineering, Kalikiri, Annamayya Dt., as an Assistant Professor(Ad-hoc) in ECE Department, since April 2022.(1.6 years)
  • Worked as an Assistant Professor in Electronics & Communication Engineering Department at Sreenivasa Institute of Technology and Management Studies, Chittoor, Chittoor Dt., from June 2019 to April 2022.(3 years)
  • Worked as an Assistant Professor in Electronics & Communication Engineering Department at Mother Theresa Institute of Engineering and Technology, Palamaner from June 2016 to June 2019.(3 Years)
  • Worked as an Assistant Professor in Electronics & Communication Engineering Department at Sri Sai Institute of technology and science, Rayachoty from November 2009 to June 2016 (6Years – 7Months)
  • Worked as an Associate Lecturer in Electronics & Communications Department at Vasavi polytechnic, Banaganapalle from September 2005 to November 2007. (2 Years)

SUBJECTS HANDLED:

  • VLSI Design
  • Switching Theory and Logic Design
  • Antennas and Wave Propagation
  • Cellular and mobile Communications
  • Analog Communications
  • Digital Communications
  • Optical Communications
  • Wireless Communication and Networks
  • Algorithms for VLSI
  • Hardware and Software Co-design
  • Electronic Devices and Circuits
  • Electromagnetic Theory and Transmission lines
  • Probability Theory and Stochastic Process
  • Digital Circuits and Systems
  • Mechatronic System
  • Universal Human Values

RESEARCH INTEREST:

  • VLSI Design
  • Low power VLSI
  • Design for Testability
  • Digital Electronics

CAREER EXCELLENCE:

  • Successfully completed the NPTEL course “NBA Accreditation and Teaching and Learning in Engineering(NATE) with score of 67%.
  • Successfully completed the NPTEL course “Introduction to machine learning” with score of 55%.
  • Qualified for Assistant professor in UGC-NET June 2021
  • Qualified in GATE-2007
  • Qualified Lectureship in UGC-NET in December 2012 Qualified in APRCET-2018.

ADMINISTRATION WORKS:

  • Worked as Additional controller of examinations-2
  • Student Counselor
  • Project Coordinator
  • Student Discipline Coordinator
  • Worked as an “Institute NAAC coordinator for C3 – Research, Innovations and Extension” in MTIET, Palamaner.

TRAINING COURSES/ ONLINE COURSES/ FDPS/ WORKSHOPS/ SEMINARS, QUIZZES AND WEBINARS ATTENDED – 26

  • Training Courses – 01
  • FDPs – 14
  • National Workshops – 04
  • STTPs – 02
  • Webinars – 03
  • Quizzes – 02
  • Total – 26

TRAINING COURSES – 01

  • Attended a “Two weeks training program on Low power VLSI conducted by RGMCET , Nandyal in June 2011.

FDPs – 14

  • Participated Three day faculty development program on eSim organized by Vellore institute of technology, Chennai from 14-05-2020 to 16-05-2020.
  • Participated one week faculty development program on Research Challenges and Emerging Trends in ECE organized by Ramachandra College of Engineering, Eluru from 27-05-2020 to 01-06-2020.
  • Participated one week faculty development program on Recent trends Research Areas in applied VLSI and Advanced Communications organized by VVIT, Nambur, Guntur(dt) from 08-06-2020 to 12-06-2020.
  • Participated Five day faculty development program on Recent Developments in Communication, Networking & Research opportunities organized by SITAMS, Chittoor from 23-06-2020 to 27-06-2020.
  • Participated two day program on How to Write a Research Paper organized by Matterhere from 20-06-2020 to 21-06-2020.
  • Participated one day faculty development program on Research Methodology-Methods & Best Practices organized by Santhiram Engineering College, Nandyal on 07-05-2020 in collaboration with Nethaji Subhas institute of Technology,Patna.
  • Participated in five day live online faculty development program on Artificial intelligence and its applications organized by Tirumala engineering college, Narasaraopet during 2805-2021 to 01-06-2021.
  • Participated in five day online faculty development program on Challenges and advances in communication system for 5G organized by Lakkireddy balireddy college of engineering ,Mylavaram during 14-06-2021 to 18-06-2021.
  • Participated in a 40-hour on line faculty development programme on “NANO SCALE DEVICES & INTERNET OF THINGS FOR ENGINEERING APPLICATIONS” sponsored by ministry of electronics and information technology, GOI organized by department of electronics and communication engineering, NITW and E&ICT academy, NIT Warangal during15th-25th February, 2022.
  • Participated in a five day online FDP on the theme “inculcating Universal Human values in Technical education” organized by All India Council for Technical Education(AICTE) from 19th September to 23rd September 2022.
  • Participated in a four day FDP on “21st Century Skills & Teaching methodologies” Conducted by Andhra Pradesh State Council of Higher Education(APSCHE), Mangalagiri, AP., in association with Commonwealth Educational Media Centre for Asia(CEMCA) and Sri Padmavathi Mahila Visvavidyalayam, Tirupati, A.P from 7th to 10th of December 2022.
  • Participated in a five day online FDP on “Design of High frequency Antennas for real time Applications(DHARA-2023)” jointly Organized by the Department of ECE of GMR Institute of Technology Rajam and the Department of ECE of VR Siddhartha Engineering College, A.P on 14-18 March 2023.
  • Participated in a five day online FDP on” Recent Trends and Applications of Nano electronics” organized by the Department of Electronics & Communication Engineering in association with Centre for Training and Learning, National Institute of Technology, during 16th -20th October,2023.
  • Participated in a seven day online FDP on Outcome based Education(OBE) organized by Nirmala College, Muvattupuzha in association with The Kerala state Higher Education Council from 10th-17th May 2023.

STTPs – 02

  • Participated one week short term training program on Emerging Technologies in Electronics & Communication Engineering from 18-05-2020 to 22-05-2020 organized by SVEC, Tirupathi in association with IETE, India.
  • Participated in five day online short term course on Research trends and practical applications on signal processing & VLSI organized by Tirumala engineering college, Narasaraopet during 18-06-2021 to 22-06-2021.

NATIONAL WORKSHOPS – 04

  • Attended a National level Work Shop on Digital signal processing algorithms & VLSI at SIETK, Puttur in March 2009.
  • Attended a Two days National level Work Shop on Advances in VLSI Design & Embedded Systems at SVCET, Chittoor in February 2013.
  • Attended a National level Work Shop on Emerging Technologies in signal processing and VLSI at SSITS, Rayachoty in April 2011.
  • Attended a National level Work Shop on Emerging trends in VLSI Design at SITAMS, Chittoor in December 2007.

WEBINARs -05

  • Participated in Webinar on Guidelines for Research Paper Writing and Publishing on 1206-2020 organized by SITAMS, Chittoor.
  • Participated in Webinar on Research Challenges Career opportunities in VLSI held on 0606-2020 organized by NBKRIT, Vidyanagar.
  • Participated in Webinar on Outcome-Based Education held on 16-06-2020 organized by Audisankara group of institutions, Gudur.
  • Participated in the Webinar Impact of Covid-19 on the development of Rural EconomyChallenges and Opportunities organized by LEAD INDIA Foundation and JNTUA on 2707-2020.
  • Participated in the Webinar on Microsoft Team organized by VIT, Chennai on 12-09-2020.

QUIZZES -02

  • Participated in world telecommunication day online Quiz organized by IEI-ELC and SEC-IIC ON 17-05-2020.
  • Participated and successfully completed in Faculty skill test on VLSI organized by DIET, Vijayawada on 28-05-2020.
  • Participated and successfully completed in ECE Quiz-2020 organized by NRIIT, Guntur on 01-06-2020.

INTERNATIONAL JOURNALS:

  • Published the paper titled “Biased charge reuse Technique in Non Parallel Circuit with efficient logic gates” in IJSETR.
  • Published the paper titled “An application specific reconfigurable architecture diagnosis fault in the LUT of cluster based FPGA” in IJMETMR.
  • Published the paper titled “Data encoding techniques for low power consumption in network on chip” in IJSETR.
  • Published the paper titled “A Low power decoupled 8T process” in IJIRS
  • Published the paper titled ”VLSI Architecture of Configurable Low Complexity Hard Decision Viterbi Decoder” in UGC approved IJR.
  • Published the paper titled ”novel approach of power reduction in multiplexer design” in UGC approved JICR.
  • Published the paper titled ”An Efficient Design of Optimized low Power Dual Mode Logic for Full Adder Design” in UGC approved JICR.
  • Published the paper titled “Low Power Digital Circuit Design Using Asynchronous Logic” in UGC approved Journal TIJER.
  • Published the paper titled “A Novel Methodology in Low Power Asynchronous Circuit Design” in UGC approved Journal JICR.

CONFERENCES:

  • Presented a paper in National Level Conference on Low Power VLSI at VITS, Hyderabad in April 2013.
  • Presented a paper in International Conference on advanced communication systems at SVCE, Tirupati in October 2017.
  • Presented a paper in National Level Conference on Recent Advances in Technology Engineering at VEMU Institute of Technology, Chittoor in August 2021.
  • Published a paper in IEEE conference on Signal Processing, Computing and Control2K21.

REFERENCE PERSONS:

  • Mr.N.VENKATA RAMANA, Scientist-D, DRDO, Chennai Phone No: +91- 90003124840.
  • Dr.Y.MURALI MOHAN BABU, Professor & HOD in ECE Department. Chadalavada Ramanamma Engineering College, Tirupati Phone No: +91- 8187826124

PERSONAL PROFILE:

  • NAME: G.MUNIRATHNAM
  • FATHER NAME: G.GANGAIAH
  • DATE OF BIRTH: 09-06-1984
  • MARITAL STATUS: Married
  • LANGUAGES KNOWN: Telugu, English, Tamil
  • STRENGTHS: Hardworking, Optimistic, Adoptive nature
  • PERMANENT ADDRESS: 5Rajulakandriga (V), Gundrarajukuppam (P), Nagari (M), Chittoor (D)